<{CPSR-SPSR}>=<{7}I{0}><{6}F{0}> ; ; Interrupt Disable bits ; <>> ; Disable the IRQ ; <>> ; Disable the IRQ ; <>> ; Disable the Fast IRQ ; <>> ; Disable the Fast IRQ <{CPSR-SPSR}<{31-28}cond}>>=<{31}N{0}><{30}Z{0}><{29}C{0}><{28}V{0}> ; ; Condition Code Flags ; <>> ; (No meaning) ; <>> ; Bit 31 of the result has been set. (Indicates a negative number in signed operations) ; <>> ; Result is all zeros. ; <>> ; Result of operation was zero. ; <>> ; After Shift operation '1' was left in carry flag. ; <>> ; Result was greater than 32 bits. ; <>> ; (No meaning) ; <>> ; Result was greater than 31 bits. (Indicates a possible corruption of the sign bit in signed numbers) ; ; ; <{31}N{31-0}><{30}Z><{29}C><{28}V><{7}I><{6}F><{5}T><{4-0}Mode> ; ; ; ; <{31}N><{30}Z><{29}C><{28}V><{7}I><{6}F><{5}T><{4-0}Mode> ; ; ; Negative flag ; <{0}1> ; Negative result from ALU flag ; ; Zero flag ; <{0}1> ; Zero result from ALU flag ; ; Carry flag ; <{0}1> ; ALU operation Carried out ; ; oVerflow flag ; <{0}1> ; ALU operation oVerflowed ; ; IRQ flag ; <{0}1> ; disables the IRQ ; ; Fast IRQ flag ; <{0}1> ; disables the FIQ ; ; T Bit (Architecture v4T Only) ; <{0}0> ; Processor in ARM state ; <{0}1> ; Processor in Thumb state ; ; ; ; ; ; Processor Mode ; <{4-0}> ; define the processor Mode ; ; ARM Instruction Set Format ; <{31-28}cond><{27-26}00><{25}I><{24-21}opcode><<20>S><{19-16}Rn><{15-12}Rd><{11-0}Operand2> ; Data processing / PSR Transfer ; <{31-28}cond><{27-22}000000><{21}A><{20}S><{19-16}Rd><{15-12}Rn><{11-8}Rs><{7-4}1001><{3-0}Rm> ; Multiply ; <{31-28}cond><{27-23}00001><{22}U><{21}A><{19-16}RdHi><{15-12}RdLo><{11-8}Rs><{7-4}1001><{3-0}Rm> ; Long Multiply (v3M / v4 only) ; <{31-28}cond><{27-23}00010><{22}B><{21-20}00><{19-16}Rn><{15-12}Rd><{11-8}0000><{7-4}1001><{3-0}Rm> ; Swap ; <{31-28}cond><{27-26}01><{25}I><{24}P><{23}U><{22}B><{21}W><{20}L><{19-16}Rn><{15-12}Rd><{11-0}Offset> ; Load/Store Byte/Word ; <{31-28}cond><{27-25}100>{25}<{24}P><{23}U><{22}S><{21}W><{20}L><{19-16}Rn><{15-0}Register List> ; Load/Store Multiple ; <{31-28}cond><{27-25}000><{24}P><{23}U><{22}1><{21}W><{20}L><{19-16}Rn><{15-12}Rd><{11-8}Offset1><{7}1><{6}S><{5}H><{4}1><{3-0}Offset2> ; Halfword transfer : Immediate offset (v4 only) ; <{31-28}cond><{27-25}000><{24}P><{23}U><{22}0><{21}W><{20}L><{19-16}Rn><{15-12}Rd><{11-8}0000><{7}1><{6}S><{5}H><{4}1><{3-0}Rm> ; Halfword transfer : Register offset (v4 only) ; <{31-28}cond><{27-25}101><{24}P><{23}U><{22-20}101><19}L><{18-0}Offset> ; Branch ; <{31-28}cond><{27-24}0001><{23-20}0010><{19-16}1111><{15-12}1111><{11-8}1111><{7-4}0001><{3-0}Rm> ; Branch Exchange (v4T only) ; <{31-28}cond><{27-25}110><{24}P><{23}U><{22}N><{21}W><{20}L><{19-16}Rn><{15-12}CRd><{11-8}CPNum><{7-0}Offset> ; Coprocessor data transfer ; <{31-28}cond><{27-24}1110><{23-20}Op1><{19-16}CRn><{15-12}CRd><{11-8}CPNum><{7-5}Op2><{4}0><{3-0}CRm> ; Coprocessor data operation ; <{31-28}cond><{27-24}1110><{23-21}Op1><{20}L><{19-16}Crn><{15-12}CRd><{11-8}CPNum><{7-5}Op2><{4}1><{3-0}Crm> ; Coprocessor register transfer ; <{31-28}cond><{27-24}1111><{23-0}SWI Number> ; Software interrupt ; ; Register ; r0 ; Register 0 ; r1 ; Register 1 ; r2 ; Register 2 ; r3 ; Register 3 ; r4 ; Register 4 ; r5 ; Register 5 ; r6 ; Register 6 ; r7 ; Register 7 ; r8 ; Register 8 ; r9 ; Register 9 ; r10 ; Register 10 ; r11 ; Register 11 ; r12 ; Register 12 ; r13 ; Register 13 ; r14 ; Register 14 ; r15 ; Register 15 ; r8_fiq ; Register 8 (Fast IRQ Mode) ; r9_fiq ; Register 9 (Fast IRQ Mode) ; r10_fiq ; Register 10 (Fast IRQ Mode} ; r11_fiq ; Register 11 (Fast IRQ Mode) ; r12_fiq ; Register 12 (Fast IRQ Mode) ; r13_fiq ; Register 13 (Fast IRQ Mode) ; r14_fiq ; Register 14 (Fast IRQ Mode) ; r13_svc ; Register 13 (Service Mode) ; r14_svc ; Register 14 (Service Mode) ; r13_abt ; Register 13 (About Mode) ; r14_abt ; Register 14 (About Mode) ; r13_irq ; Register 13 (IRQ Mode) ; r14_irq ; Register 14 (IRQ Mode) ; r13_undef ; Register 13 (Undefined Mode) ; r14_undef ; Register 14 (Undefined Mode) ; cpsr ; C Program Status Register ; spsr_fiq ; S Program Status Register (Fast IRQ mode) ; spsr_svc ; S Program Status Register (Service mode) ; spsr_abt ; S Program Status Register (About mode) ; spsr_irq ; S Program Status Register (IRQ mode) ; spsr_undef ; S Program Status Register (Undefined mode) <+-> ; ; ; + ; Positive ; - ; Negative ; ; Condition Codes ; CS ; Carry Set ; CC ; Carry Clear ; EQ ; Equal (Zero Set) ; NE ; Not Equal (Zero Clear) ; VS ; Overflow Set ; VC ; Overflow Clear ; HI ; Higher Than ; HS ; Higher or Same ; LO ; Lower Than ; LS ; Lower Than or Same ; GT ; Greater Than ; GE ; Greater Than or Equal ; LT ; Less Than ; LE ; Less Than of Equal ; MI ; Minus (Negative) ; PL ; Plus (Positive) ; ; Data Access ; # ; Immediate ; Rm ; Register ; Rm, LSL # ; Logical Shift Left Immediate ; Rm, LSL Rs ; Logical Shift Left Register ; Rm, LSR # ; Logical Shift Right Immediate ; Rm, LSR Rs; Logical Shift Right Register ; Rm, ASR # ; Arithmetic Shift Right Immediate ; Rm, ASR Rs ; Arithmetic Shift Right Register ; Rm, ROR # ; Rotate Right Immediate ; Rm, ROR Rs ; Rotate Right Register ; Rm, RRX ; Rotate Right with Extend ; ; Memory Access ; [Rn, #<+->] ; Immediate Offset ; [Rn, Rm] ; Register Offset ; [, Rm, #]; Sealed Register Offset ; [Rn, #<+->]! ; Immediate Pre indexed ; [Rn, Rm]! ; Register Pre indexed ; [Rn, Rm, #]; Scaled Register Pre indexed ; [Rn], #<+-> ; Immediate Post indexed ; [Rn], Rm ; Register Post indexed ; [Rn], Rm, , # ; Scaled Register Post Indexed ; ; ; LSL ; Logical Shift Left ; LSR ; Logical Shift Right ; ASR ; Arithmetic Shift Right ; ROR ; Rotate Right ; RRX ; Rotate Right with Extend ; ; ARM Instructions ; ADC Rd, Rn, ; Add with Carry ; ADD Rd, Rn. ; Add ; AND Rd, Rn, ; Bitwise AND ; B ; Branch ; BL ; Branch and Link ; CMP Rn, ; Compare ; EOR Rd, Rn, ; Exclusive OR ; LDR Rd, ; Load Register ; LDRB Rd, ; Load Register Byte ; MOV Rd, ; Move ; MVN Rd, ; Move Negative ; ORR Rd, Rn, ; Bitwise OR ; SBC Rd, Rn, ; Subtract with Carry ; STR Rd, ; Store Register ; STR Rd, Rn, ; Store Register Byte ; SUB Rd, Rn, ; Subtract ; SWI ; Software Interrupt ; SWP Rd, Rm, [Rn] ; Swap ; SWPB Rd, Rm, [Rn] ; Swap Byte